Various Projects Find Hidden SDR Capabilities in ESP32 Microcontrollers
nkw
197 points
30 comments
October 01, 2026
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Discussion Highlights (7 comments)
mallets
So many $1 wireless ICs have a powerful "SDR", but will never be documented due to certification/compiliance/export-control reasons. The projects listed here rightly limited the scope to RX-only but Espressif might be forced to "patch" this away if arbitrary TX too is possible (or starts making headlines). Hope it doesn't come to that, more cheap options for RF-to-bits is always welcome. On a technical note, not much I can find about the signal quality. Phase noise, images, DC Offset, etc. Have to get my hands on one, ESP32-S31 seems promising.
BlackRabbit1
As far as I follow the research process it's currently quite difficult to get all data (like the 80MSPS@10-Bit showcase on Reddit) to a computer without a FPGA+USB3. With the new ESP32-S31 we most likely can extract the I/Q data over its new 1 GBit/s interface. Guessing something around 20-40MSPS should work. These hack will most likely will be a revolution for 13cm ham radio. With the new 5GHz ESP32 modules most likely also for 5cm. As all Espressif components are WiFi-qualified we can expect a very very stable and robust radio. I ordered a few and waiting for Ali to deliver them to my lab.
ErroneousBosh
> undocumented feature that lets the firmware bypass the fixed WiFi and Bluetooth functionality and instead capture raw IQ baseband samples So kind of like those TV USB sticks that you can adapt into proper SDRs?
xd1936
Very exciting! > However, the current prototype uses the FPGA to clock the ESP32, which results in poor phase noise. Looks like this was solved five days ago: https://github.com/h0m3us3r/eSpDR/commit/41a0ffe279119df942e...
drtz
Since I'm a little slow and it took me a minute: SDR in this context is software defined radio.
cellular
Any way to finagle a LORA type system (ultra reliable using precise timing) using a few of these on each end?
mrheosuper
The ESP32S3 support PSRAM, can we redirect the sample to PSRAM, then hooking Logic Analyzer on PSRAM, thus getting the sample directly, not through any digital interface. (There is cache before PSRAM, but should be trivial to sync).